Latch‑Up

A low‑impedance, self‑sustaining conduction state in CMOS integrated circuits produced by activation of parasitic p‑n‑p and n‑p‑n transistor pairs (a parasitic thyristor or SCR) that creates a current path between supply rails; it is triggered by injection of charge or overvoltage and persists until the current is removed or limited, potentially causing thermal damage or device failure.